This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-075511, filed Mar. 16, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having an element isolation region and a transistor, and a method of manufacturing the semiconductor device, and particularly relates to a semiconductor device in which a contact is formed in the vicinity of the element isolation region and the transistor and the method of manufacturing the semiconductor device.
2. Description of the Related Art
Conventionally, as for a semiconductor memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory) in which data is electrically written/erased is known. In the EEPROM, a memory cell is arranged respectively at the intersection where a row line and a column line are crossed each other to form a memory array. Generally, a MOS transistor having a laminated gate structure in which a floating gate and a control gate are laminated is employed for a memory cell.
As a method suitable for a memory having a large capacity among EEPROMs, a NAND type EEPROM as shown in FIG. 33 is known. Here, FIG. 31 is a view showing a cross section taken along the line XXXIxe2x80x94XXXI in FIG. 33, and FIG. 32 is a view showing a cross section taken along the line XXXIIxe2x80x94XXXII in FIG. 33.
As shown in FIGS. 31 and 32, a plurality of memory cell transistors are connected in series in a memory cell array of a NAND type EEPROM, and a drain side selecting gate transistor 53 is connected to its one side, and a source side selecting gate transistor 54 is connected to the other side. A well 51 is formed on part of a semiconductor substrate 50, and a plurality of element regions 55 in a stripe shape are formed therein. Each element region 55 is Isolated by an element isolation region 56. On each element region 55, a plurality of cell transistors having a laminated gate structure are formed in a line along the extension direction of the stripe, and a plurality of cell transistors are arranged in a matrix shape on the entire surface of the plural element regions 55.
As shown in FIG. 31, each memory cell has a gate electrode portion 52 formed on a gate insulating film 57 located on the element region 55, and the gate electrode section 52 is configured by laminating a floating gate electrode 58 which becomes an electric charge accumulation layer, an inter-gate insulating film 59, a control gate electrode 60 and a gate protection film 71. Furthermore, the control gate electrode 60 becomes, as shown in FIG. 33, a word line 61 by being shared with the other gate electrodes in the row direction.
In each element region, a source and a drain of each memory cell are connected with each other via a source/drain diffusion layer region 62. In each element region, a source and a drain of each memory cell are a common region with a drain and a source of the adjacent memory cell, thereby connecting a plurality of memory cells in series to form one NAND cell memory cell unit) in each element region.
The drain side selecting gate transistor 53 and the source side selecting gate transistor 54 are connected, respectively, to one end and the other end in the direction of a bit line of each NAND cell (i.e., extension direction of stripe). The respective selecting gate transistors 53 and 54 have a gate electrode formed on the gate insulating film 57, and connected to the NAND cell via the diffusion layer region 62. Moreover, the selecting gate transistors 53 and 54 are configured so as to be capable of applying a potential to the floating gate electrode. The selecting gate transistors 53 functions in the same manner as a general MOSFET, and its laminated layer gate structure is similar to that of the memory cell transistor.
Moreover, a bit line contact diffusion layer 62 is formed on the side of the drain side selecting gate transistor 53 opposing to the NAND cell within the element region 55. A bit line contact 63 is connected to this bit line contact diffusion layer 62. This bit contact 63 is connected to a bit line 64.
A post-oxidation film 65 is formed on the surfaces of the respective gates 52, 53 and 54. Then, a silicon nitride film 67 is formed On the surface of the post-oxidation film 65, the source/drain diffusion layer 62, the drain contact diffusion layer 62, and a source diffusion layer 66 of the source side selecting gate 54, that is, on the diffusion layer 66 opposite to the memory cell. An interlayer insulating film 68 is formed on the surface of the silicon nitride film 67 and further the surface thereof is flattened.
Here, the bit line contact 63 is formed in the gate insulating film 57, the silicon nitride film 67 and the interlayer insulating film 68. The bit line 64 is formed on the interlayer insulating film 68. The bit line 64 is independently formed in each NAND cell formed in parallel with each other in the direction of the column (i.e., extension direction of stripe).
Moreover, a source line (not shown) is connected to the source diffusion layer 66 formed on the side of the source side selecting gate transistor opposing to the NAND cell. The source line is formed on the upper layer above the gate electrode, the contact is connected to a layer portion (not shown) to which one end of the floating gate is extended. The source line is formed commonly in a NAND cell formed in parallel in the direction of the column.
As shown in the cross sectional view shown in FIG, 32, the plural element isolation regions 56 define the plurality of element regions 55 in the well 51 on the semiconductor substrate 50. The bit line contact 63 is connected to the entire surface of the element regions 55 defined by the element isolation regions 56. The silicon nitride film 67 is formed on the element isolation region 56, and the interlayer insulating film 68 is formed thereon. The bit line contact is formed in the interlayer insulating film 68 and the silicon nitride film 67. The bit line wiring 64 is formed on the bit line contact 68.
Next, a method of manufacturing a conventional semiconductor device shown in FIG. 31 through FIG. 33 will be described below with reference to FIG. 34 through FIG, 36.
First, as shown in FIG. 34, the element region 55 surrounded by an element isolation region (not shown) is formed on the semiconductor substrate 50 made of silicon, the gate insulating film 57, the floating gate electrode film layer 58 and an inter-gate insulating film layer 59 are formed thereon, and the control gate electrode layer 60 and the gate protection film layer 70 are deposited thereon. Subsequently, the memory cell gate 52 and the selecting gates 53 and 54 are formed by patterning these layers using a lithography method and etching them.
Next, the post-oxidization is performed and the post-oxidization film 65 is formed around the gate electrode of the laminated structure.
Then, the source/drain diffusion layer 62, the drain contact diffusion layer 62 and the source diffusion layer 66 are formed by performing the ion implantation of an impurity.
After that, as shown in FIG. 35, for example, the silicon nitride film 67 on the order of 40 nm in thickness, for example, is deposited. At this time, the silicon nitride film 67 is formed so as to also cover the gate electrode sidewall.
Furthermore, the interlayer insulating film 68 is deposited until it is embedded between the gate electrodes, and subsequently, the interlayer insulating film 68 is flattened by performing the re-flowing using a CMP (Chemical Mechanical Polishing) and a thermal processing.
Next, as shown in FIG. 36, a contact hole 71 for contact with the bit line contact diffusion layer 62 adjacent to the drain side selecting gate 53 is formed in the interlayer insulating film 68, the silicon nitride film 61 and the gate oxide film 57.
Next, subsequently, a metal or a low resistive semiconductor is embedded in the contact hole 71, and then, a semiconductor device as shown in FIG. 31 is completed by forming metal wirings.
As described above, in a conventional semiconductor device, after the formation of the gate electrode, the silicon nitride film 67 covering the entire surface is formed. The reason why the silicon nitride film 67 is needed will be described below.
As shown in FIG. 32 and FIG. 33, the bit line contact 63 is designed so that there is no margin with respect to the element region 55. Specifically, the bit line contact 63 is formed with respect to the element region 55 so as to fit the rim of its width. Note that there are some cases where the bit line contact 63 is designed so as to be wider than the element region 55. This is for the sake of being capable of diminishing the area of the cell array as narrow as possible.
In the semiconductor device, it must be made so that the bit line contact does not penetrate within the element isolation region even when the formation position of the contact is intruded into the element isolation region by the reasons that the deviation of the positioning of a mask or the like occurs. This is because it causes the occurrence of the junction leak current in that portion or the lowering of the breakdown voltage of the element if the bit line contact penetrates the element isolation region.
In the case of a semiconductor device without a silicon nitride film, as shown in FIG. 21, it may be possible that the contact hole 71 penetrate the element isolation region 56 since the insulating film of the element isolation region 56 is also etched when the interlayer insulating film 68 is etched at the time of opening the contact hole 71 for bit line contact. In this case, the portion where the bit line contact 63 has intruded within the element isolation region 56 and formed is conducted to the element region 55, that is, an electric contact is made except for the contact on the source/drain diffusion layer 62, and the characteristics of the transistor are damaged.
These are the reasons why in general, upon the etching at the time when the contact hole 71 is opened, the etching is excessively performed to some extent that the contact hole 71 is securely opened even if the variations of the process exist, and in general, since the interlayer insulating film and the insulating film of the element isolation region are formed with a silicon oxide film, it is difficult to selectively etch only the interlayer insulating film. Such a state possibly occurs when the width of the element region and the width of the bit line contact are close to each other.
In order to prevent such a phenomenon, in a conventional semiconductor device, as described above, the silicon nitride film 67 is employed. Using this, in a miniaturized semiconductor device, the etching can be stopped on the silicon nitride film 67 once even if the deviation M of the positioning has occurred as shown in FIG. 38, by having made the etching at the time of opening the contact hole the selectivity of the silicon oxide film and the silicon nitride film.
Thus, after the contact hole reaching the portion above the silicon nitride film 67 is opened, the silicon nitride film 67 is etched by changing the conditions for etching, and the silicon oxide film on the substrate is etched by further changing the conditions, thereby the contact hole 71 located above the source/drain diffusion layer is completely opened.
In this way, it can be prevented that the element isolation region 56 is largely etched by opening the bit line contact hole 71 for contact with the diffusion layer. In this way, it is prevented that the contact hole 71 penetrates the element isolation region 56 by the silicon nitride film 67 functioned as an etching stopper.
In a conventional semiconductor device as described above, the following problems occur.
In a semiconductor memory device using the conventional silicon nitride film, a large amount of hydrogen is contained in the silicon nitride film. If this hydrogen is incorporated into the silicon oxide film, the structure defect such as Sixe2x80x94H bonding or the like is easily occurred on the interface with the silicon substrate. The bonding energy of this Sixe2x80x94H bonding is weak as compared to the bonding energy of Sixe2x80x94O bonding.
Here, in a non-volatile semiconductor memory device or the like, at the time of operating the memory writing/erasing, a strong electric field is applied between the control gate and the channel, tunnel current is flown to the gate insulating film, thereby executing the operation that the electric charge is implanted to or removed from the floating gate. In such an operation, if the tunnel current is flown near the gate insulating film, an electric stress is to be added.
If a film having a large amount of hydrogen content exists in the vicinity of the gate insulating film, the structure defect such as Sixe2x80x94H bonding or the like tends to be easily occurred on the interface with the silicon substrate because the hydrogen is incorporated into the silicon oxide film.
When this structural defect is cut down by an electric stress or the like, it acts as a trap for an electric charge. Particularly, when this trap occurs on a silicon oxide film which is a gate insulating film, or on the post-oxidization film in the vicinity of the gate insulating film, or the like, it will cause the deterioration of the electric characteristics such as the variation of threshold voltage of the transistor, the lowering of breakdown voltage of the silicon oxide film or the like.
Moreover, when the electric charge to the trap of the post-oxidization film covering the surface of the source/drain diffusion layer is captured, the diffusion layer near the surface of the substrate is depleted and as a result, a parasitic resistance of the source/drain is increased, the lowering of the on-current of the transistor may occur.
Moreover, it is known in general that also in the silicon nitride film, a large number of traps with respect to the electric charge exist. Particularly, when the electric charge is captured by the trap of the silicon nitride film covering the surface of the source/drain diffusion layer, the diffusion layer near the surface of the substrate is depleted, as the result, the parasitic resistance of the source/drain is increased, the lowering of the on-current of the transistor may occur.
Moreover, when the electric charge is captured in the silicon nitride film near the gate insulating film, it will cause the deterioration of the electric characteristics such as the variation of the threshold voltage of the transistor, the lowering of the silicon oxide film breakdown voltage.
These problems is particularly significant when the gate length is smaller than about 0.2 xcexcm Specifically, it is significant when the ratio of the silicon oxide film, post-oxidization film and silicon nitride film in which traps occur near the gate insulating film occupying the entire gate is large.
As described above, the silicon nitride film is needed for etching the contact hole, while the adverse influence of the silicon nitride film is seen with respect to the electric characteristics. Therefore, it has been difficult to realize the enhancement of both of the yield and reliability of the semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate; a first gate electrode formed on the semiconductor substrate; a first diffusion layer formed in the semiconductor substrate, the first diffusion layer being provided under one of opposite side portions of the first gate electrode; a second diffusion layer formed in the semiconductor substrate, the second diffusion layer being under another one of the opposite side portions of the first gate electrode; a second gate electrode formed on the semiconductor substrate, a side portion of the second gate electrode being provided on the second diffusion layer; a first insulating film formed on the semiconductor substrate, the first insulating film covering the first gate electrode, the second gate electrode, the first diffusion layer and the second diffusion layer, a portion of the first insulating film being embedded between the first gate electrode and the second gate electrode, a thickness of a portion of the first insulating film, which is provided on the first diffusion layer, being thinner than a thickness of the portion of the first insulating film, which is embedded between the first gate electrode and the second gate electrode, the first insulating film not containing nitrogen as a major component; a second insulating film formed on the first insulating film; an interlayer insulating film formed on the second insulating film, a major component of the interlayer insulating film being different from a major component of the second insulating film; and a contact electrode connected to the first diffusion layer, the contact electrode being formed in the first insulating film, the second insulating film and the interlayer insulating film.